1. Field of the Invention
The present invention relates to a semiconductor logic circuit such as a Bipolar CMOS (BiCMOS) gate and the like used under a low power source voltage.
2. Description of the Prior Art
Conventionally, a BiCMOS type logical gate in which a bipolar transistor and a MOS transistor are formed on a same semiconductor substrate is used in an element which requires high velocity as a logical gate and whereby a large drive ability can be obtained.
FIG. 1 is a circuit diagram for a conventional BiCMOS inverter.
As shown in the drawing, in this BiCMOS inverter, output of a pull-up section and a pull-down section for driving a load consist of a bipolar (NPN) transistors 101, 102 respectively. Currents of bases of the bipolar transistors 101, 102 are driven or controlled by the drain current of a P channel type MOS transistor (hereinafter P-MOS) 103 and an N channel type MOS transistor (hereinafter N-MOS) 104. Also, when an input signal VIN is switched from the H to the L level and from a Low level( L level) to a High level(H level), the base current is pulled out by an N-MOS Transistor 105 and an N-MOS 106 respectively.
In using this BiCMOS inverter, when the input signal VIN transmitted to an input node N1 is at the L level, the P-MOS Tr 103 is ON and the base of the bipolar transistor 101 is charged to a power source voltage VCC. As a result, the bipolar transistor 101 is turned ON and an output node N2 is charged. At this time the N-MOS 104 is OFF, therefore the bipolar transistor 102 is also OFF. Accordingly, the output Vout of the output node N2 is pulled H level.
In addition, when the input signal VIN is at the H level, the N-MOS 104 is ON and the base of the bipolar transistor 102 is charged. As a result, the bipolar transistor 102 is turned ON and the output node N2 is discharged. At this time the P-MOS 103 is OFF, therefore the bipolar transistor 101 is also OFF. Accordingly, the output Vout of the output node N2 is pulled L level.
As described above, the BiCMOS gate has a high speed characteristics superior to a CMOS gate comprising a PMOS transistor 111 and a NMOS transistor 112 which are connected complementarily shown in FIG. 2, because bipolar transistors with a large drive ability are used for driving the in the pull-up operation and the pull-down operation at the Vout in the semiconductor logic circuit.
However, as the miniaturization of MOS transistors has proceeded in recent years, there has been a tendency to reduce the power source voltage VCC. For example, during the operation of the BiCMOS inverter shown in FIG. 1, a voltage potential VGS1 between the gate and the source of the P-MOS 103 used for pull-up operation to drive loads through the node N2 becomes VGS1=VIN-VCC. Also, a voltage potential VGS2 between the gate and the source of the N-MOS 104 for driving the bipolar transistor 102 used for pull-down operation to drive the loads through the node N2 becomes VGS2=VIN-VSS-VBE (where VBE is the voltage between the base and emitter of the bipolar transistor 102).
In the case where an operation is considered at a low power source voltage VCC of 3.3 Volts as compared to an operation at a comparatively high power source voltage VCC of 5 Volts, the ratio of the base-emitter voltage VBE (about 0.8 Volts) of the transistor 102 to the gate source voltage VGS of the MOS transistor 104 becomes large.
As a result, there is the problem that the drain current of the N-MOS transistor 104 for driving the bipolar transistor 102 used for the pull-down operation becomes extremely small, the drive ability for the pull-down operation suddenly drops, and delay time of this gate is caused in the above-mentioned BiCMOS gate shown in FIG. 1.
Accordingly, to eliminate this type of problem described above, a BiNMOS gate consists of a bipolar transistor and a N-MOS transistor as an output section, as shown in FIG. 3, is commonly known. FIG. 3 shows one example of this BiNMOS inverter including the BiNMOS gate.
As illustrated in the drawing, a section for the pull-up operation of this BiNMOS inverter has a bipolar transistor 121 in the same manner as in the BiCMOS inverter shown in FIG. 1. The base of the bipolar transistor 121 is driven by the drain current of a P-MOS 122 transistor. When the input signal VIN is switched from the H to L level, the base current is pulled out by an N-MOS transistor 123. In addition, a section of the pull-down operation of the BiNMOS inverter consists of an N-MOS transistor 124 whose gate is directly connected to the input node N1 only. Specifically, because in this BiNMOS gate the drive ability of the pull-down output of the BiNMOS gate is reduced along with the reduction of the power source voltage VCC as outlined above, the section of the pull-down operation in the BiNMOS inverter is formed from the N-MOS transistor 124 only in order to solve this problem.
During the operation of this BiNMOS inverter shown in FIG. 3, a voltage potential VGS3 between the gate and the source of the P-MOS transistor 122 becomes VGS3=VIN-VCC, and a voltage potential VGS4 between the gate and the source of the N-MOS transistor 124 on the section side of the pull-down operation becomes VGS4=VIN-VSS. As a result, as in the above-mentioned BiCMOS gate shown in FIG. 1, the magnitude of the drive ability of the BiNMOS inverter shown in FIG. 3 is not affected by the relative magnitude of the source voltage VCC and the base-emitter voltage VBE.
Accordingly, by means of the BiNMOS gate shown in FIG. 3, the reduction in the gate delay which accompanies the reduction in the source voltage VCC can be reduced further than for the BiCMOS gate shown in FIG. 1.
However, in the circuit configurations of FIG. 1 and FIG. 3 outlined above, the output Vout is not charged (discharged) up to the source potential (or the ground potential). Specifically, there is the problem that a full swing operation is not carried out.
To explain in more detail, when the input signal VIN is at the L level in the BiCMOS gate shown in FIG. 1, the base of the bipolar transistor 101 is charged to the source voltage VCC, and the output Vout is only charged to Vout=VCC-VBE. Also, when the input signal VIN is at the H level, the output Vout from the bipolar transistor 102 is discharged to the same potential as the base of the bipolar transistor 102 and is not discharged to the ground level.
On the other hand, in the BiNMOS gate shown in FIG. 3, the pull-down operation in the BiNMOS inverter undergoes a full swing, and the pull-up operation is only charged to Vout=VCC-VBE in the same manner as for the BiCMOS gate shown in FIG. 1.
Improved models of the above-mentioned BiCMOS gate (FIG. 1) and BiNMOS gate (FIG. 3) for which a full swing operation is not performed are shown in FIG. 4, FIG. 5, and FIG. 8.
FIG. 4 is a circuit diagram showing another conventional BiNMOS gate. Like reference numerals designate parts identical to or corresponding to those illustrated in FIG. 1.
This BiCMOS gate shown in FIG. 4 is a modification the BiCMOS gate shown in FIG. 1 in order to perform a full swing operation.
Specifically, a COS inverter 131 is connected in parallel to the BiCMOS gate shown in FIG. 1. Due to the operation of the inverter 131, pull-up operation performs a full swing to the source voltage VCC, and the pull-down operation to the ground potential.
A BiCMOS gate of this configuration has been proposed which is a modification of the BiCMOS gate shown in FIG. 5. Specifically, a PNP transistor 141 has been substituted for the pull-down operation of the NPN bipolar transistor. A P-MOS transistor 142 and an N-MOS transistor 143 connected in the same manner to the pull-up operation are connected to the base of the PNP transistor 141.
FIG. 7A shows the waveforms of the outputs Vout1, Vout2, and Vout3 at the each stage of an inverter gate chain wherein the BiCMOS inverter shown in FIG. 4 or FIG. 5 are connected in series in a three-stage shown in FIG. 6. This gate is operated under a source voltage VCC=3.3 volts.
FIG. 7B shows the waveforms of the outputs Vout1, Vout2, and Vout3 at the each stage of the inverter gate chain. This gate is operated under a source voltage VCC=5.0 volts.
As can be clearly understood from FIG. 7A, the pull-up waveforms at the outputs Vout1 and Vout3, and the pull-down waveform at the output Vout2 abruptly rise or fall between the time 0.14 and the time 0.2 and then these waveforms Vout1, Vout2, and Vout 3 slowly undergo a full swing by a MOS transistor 104.
FIG. 8 is a circuit diagram showing another conventional BiNMOS gate. Like reference numerals designate pans identical or corresponding to those illustrated in FIG. 3.
This BiCMOS gate shown in FIG. 8 is a modification of the BiCMOS gate shown in FIG. 3, which performs a full swing operation at the section side of pull-up operation. Specifically, a P-MOS transistor 151 for supporting the pull-up operation added to the BiNMOS inverter of FIG. 3.
The pull-up operation can perform a full swing to the source voltage VCC from operation of the P-MOS 151.
FIG. 8 shows waveforms of the outputs Vout1, Vout2, and Vout3 at the various stages of the inverter gate chain shown which connects three of the BiCMOS inverter in series shown in FIG. 8. The gate is operated under a source voltage VCC=3.3 v.
As can be clearly understood from FIG. 9, the outputs Vout1 and Vout3 in the inverter gate chain, which are pull-up waveforms, abruptly rise (from the time 0.1 to the time 0.18) from a stable level (from the time 0 to the time 0.18) and then, these waveforms slowly undergo a full swing (after the time 0.18) by a PMOS transistor 151, and are charged to the source voltage VCC. Also, the output Vout2, which is a pull-down waveform, is driven by the N-MOS 124, so that a comparatively small deterioration is exhibited in FIG. 7.
However, the following problem areas exist in the BiCMOS gate and the BiNMOS gate explained with reference to FIG. 4 to FIG. 9.
For example, the voltage region indicated as VB in FIG. 9 represents high speed charging by the bipolar transistor, and the voltage region indicated as VC represents slow charging by the MOS transistor. When the source voltage VCC is comparatively high (3.3 v to 5.0 v), the portion accounted for by VC is small in comparison with the source voltage VCC, therefore the deterioration of the gate delay attributable to a change in potential in the range VC can be ignored.
However, the miniaturization of MOS transistors is continuing, and when this is accompanied by a further lowering of the source voltage VCC (3.3 v to 2.5 v) the value of VC does not correspondingly decrease. Accordingly, the portion accounted for by VC becomes relatively large in comparison with the source voltage VCC. As a result, there is the problem that the gate delay abruptly increases.